1. Field of the Invention
The present invention generally relates to methods and systems for utilizing design data in combination with inspection data. Certain embodiments relate to a computer-implemented method for determining a position of inspection data in design data space and/or substantially accurately determining the position of a design space location on a wafer during an inspection process.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
An integrated circuit (IC) design may be developed using a method or system such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. Such methods and systems may be used to generate the circuit pattern database from the IC design. The circuit pattern database includes data representing a plurality of layouts for various layers of the IC. Data in the circuit pattern database may be used to determine layouts for a plurality of reticles. A layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. Each reticle is used to fabricate one of the various layers of the IC. The layers of the IC may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlevel dielectric, and an interconnect pattern on a metallization layer.
The term “design data” as used herein generally refers to the physical design (layout) of an IC and data derived from the physical design through complex simulation or simple geometric and Boolean operations.
A semiconductor device design is verified by different procedures before production of ICs. For example, the semiconductor device design is checked by software simulation to verify that all features will be printed correctly after lithography in manufacturing. Such checking commonly includes steps such as design rule checking (DRC), optical rule checking (ORC), and more sophisticated software based verification approaches that include process simulation calibrated to a to specific fab and process. The output of the physical design verification steps can be used to identify a potentially large number of critical points, sometimes referred to as “hot spots,” in the design.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Another important part of manufacturing yield control is determining the cause of defects on the wafer or reticle such that the cause of the defects can be corrected to thereby reduce the number of defects on other wafers or reticles. Often, determining the cause of defects involves identifying the defect type and other attributes of the defects such as size, shape, composition, etc. Since inspection typically only involves detecting defects on the wafer or reticle and providing limited information about the defects such as location on the wafer or reticle, number of defects on the wafer or reticle, and sometimes defect size, defect review is often used to determine more information about individual defects than that which can be determined from inspection results. For instance, a defect review tool may be used to revisit defects detected on a wafer or reticle and to examine the defects further in some manner either automatically or manually.
Defect review typically involves generating additional information about defects at a higher resolution using either a high magnification optical system or a scanning electron microscope (SEM). The higher resolution data for the defects generated by defect review is more suitable for determining attributes of the defects such as profile, roughness, more accurate size information, etc. Defect analysis may also be performed using a system such as an electron dispersive x-ray spectroscopy (EDS) system. Such defect analysis may be performed to determine information such as composition of the defects. Attributes of the defects determined by inspection, review, analysis, or some combination thereof can be used to identify the type of the defect (i.e., defect classification) and possibly a root cause of the defects. This information can then be used to monitor and alter one or more parameters of one or more semiconductor fabrication processes to reduce or eliminate the defects.
As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitations on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. Therefore, as design rules shrink, the population of potentially yield relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more and more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive. As such, determining which of the defects actually have an effect on the electrical parameters of the devices and the yield may allow process control methods to be focused on those defects while largely ignoring others. Furthermore, at smaller design rules, process induced failures may, in some cases, tend to be systematic. That is, process induced failures tend to fail at predetermined design patterns often repeated many times within the design. Elimination of spatially systematic, electrically relevant defects is important because eliminating such defects can have a significant overall impact on yield. Whether or not defects will affect device parameters and yield often cannot be determined from the inspection, review, and analysis processes described above since these processes may not be able to determine the position of the defect with respect to the electrical design.
Some methods and systems for aligning defect information to the electrical design have been developed. For instance, a SEM review system may be used to determine more accurate coordinates of defect locations for a sample of defects, and the defect coordinates reported by the SEM review system may be used to determine locations of defects in the electrical design. Other methods involve aligning inspection care areas (e.g., the areas of the device pattern formed on the wafer in which inspection will be performed) to the physical location of the pattern printed on the wafer. However, currently, the care areas can be aligned to the pattern printed on the wafer with an accuracy of no better than about 2 μm due to system errors and imperfections. For instance, some bright field (BF) inspection systems have coordinate accuracies of about +/−1 μm. In addition, the inspection care areas in currently used methods are relatively large and include many non-critical features as well as desired critical features. In trying to maximize the sensitivity of the inspection system to capture subtle spatially systematic “design-for-manufacturability” (DFM) defects resulting from design and process interdependencies, the system may be overwhelmed by millions of events in non-critical areas such as CMP fill regions. Detecting such nuisance defects is disadvantageous for a number of reasons. For example, these nuisance events need to be filtered out of the inspection results by post-processing of the inspection data. In addition, nuisance event detection limits the ultimate achievable sensitivity of the inspection system for DFM applications. A high rate of nuisance defect data may also overload the run time data processing capacity of the inspection system thereby reducing throughput and/or causing the loss of data.
Accordingly, it may be advantageous to develop methods and systems for aligning inspection data to design data with sub-pixel accuracy (where the size of the pixel may be on the order of the size of the geometries being inspected) such that substantially highly accurate “context” of the design data can be utilized to perform one or more context-based functions such as, but not limited to, grouping pixels in a defect detection algorithm or method, tailoring detection sensitivity, filtering nuisance defects, classifying defects, grouping defects, and sampling defects for review by using design context as part of the sampling scheme.